It is common knowledge among engineers that the best way to process analog signals would be in the digital domain. Signal processing varies from simple arithmetic operations such as adding multiple signals together to more complex operations such as implementing high order filters. Compared to analog, the digital domain presents a faster, more robust and more dynamic approach to handle signal processing. In order to perform digital processing on analog signals, these signals need to be properly converted into the digital domain with the best resolution as well as preserving the content of the signal with the least information loss.;Sigma Delta converters are the industry standards for high-resolution analog to digital converters (ADCs). To achieve this high resolution, the design requires high order integrators, multi-bit converters and complex digital filters. This results in a large size and power inefficient integrated circuit. This dissertation presents a novel analog to digital converter architecture that competes in terms of power, size and resolution with sigma delta converters. The theory behind this new architecture is deduced from half-toning in image processing. It captures the theory of error diffusion and blue noise masking used on multi-tone image processing and applies it in a similar fashion to digitize continuous analog signals.;Simulations have shown similar results for images half-toned through error diffusion and blue noise masking [17]. Moreover, there is a direct connection between error diffusion and sigma delta modulation, which inspired us to pursue the idea of developing a new ADC, the binary dithered oversampling ADC (BDO), based on blue noise dithering. We started with system level simulations to compare the performance of sigma delta to BDO and then developed proof of concept experiments to build the proper circuitry. It is important to mention that there has been a lot of work published about building simulation models to generate blue noise dither but there have not been a circuit developed to solely generate analog blue noise dither. It is true that a sigma delta modulator generates blue noise dither, but this is due to its negative feedback, which in return limits its speed. In this dissertation we are proposing a simple circuit, no negative feedback or integrators, that operates at much lower power and capable of achieving a bit resolution that is comparable to a first order sigma delta modulator.;Two generations of the BDO converter were implemented using 0.5 microm-CMOS technology to demonstrate their functionality. We also implemented a first order continuous time sigma delta modulator on the same integrated chip to compare both architectures. We compared both converters in terms of size, power, resolution and robustness. The proposed binary dithered oversampled converter was significantly smaller in size, consumed less power and achieved comparable resolution to that of the first order sigma delta modulator. In terms of robustness, sigma delta modulator can achieve higher resolution if we increase the oversampling ratio and use higher order integrators. The tradeoff here is an increase in size and power consumption in addition to facing some stability issues due to the high order integrators. On the other hand, the BDO converter can increase its resolution by optimizing some of its components, such as enhancing the high-pass filter responsible for the blue noise shaping, without radically increasing its size or power consumption.
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