RF receiver front-ends in deep sub-micron CMOS for mobile terminal.

摘要

RF receiver front-end design for the mobile terminals has become a challenging task. The need to share the receiver hardware over multiple RF frequency bands and RF standards; the drive toward reduction in external components and filters; low power consumption targets; deep sub-micron CMOS implementation for SoC applications; and high dynamic range requirements have created an imposing design challenge for the RF receiver front-end. In this research we have taken an objective look at this design challenge and addressed it at various levels.;In this research, multiple RF receiver front-ends in various deep sub-micron CMOS process technologies have been designed for various cellular standards. The designs utilize different architectures in order to assess the trade-offs involved with architecture selection. Innovative circuit design techniques and a novel compensation/calibration scheme have been presented.;Comprehensive system analysis of W-CDMA using modulated signals has been detailed in this work to illustrate the significance of system level analysis in achieving optimized RF receiver front-end design. Most notably, high dynamic range multi-standard capable designs in deep sub-micron CMOS that achieved high levels of integration by eliminating inter-stage SAW filters and sometimes external LNAs that have been otherwise used in state-of-the-art designs are demonstrated in this research.