Thermomechanical analysis of multilayered microelectronics packaging: Modeling and testing.

摘要

Reliability is always an extremely important issue in microelectronics packaging. In the microelectronics packaging, materials with different Coefficients of Thermal Expansion (CTE) and mechanical properties are bonded together with solder or epoxy to form laminated structures. The reliability of the system depends on the reliability of the interconnections for all components.; The Pb/Sn eutectic solder alloy is the most commonly used joining material in microelectronics packaging. Micro-structural coarsening (phase growth) is considered to be closely related to thermo-mechanical fatigue failure which has been a reliability concern for solder joints. A comparison of computational simulations for three phase growth models and test data has been presented in this dissertation. Results indicate that the quadratic power phase growth model best fits the test data.; The CTE mismatch of the connected layers causes high thermal stresses at the interfaces, especially near the free edges, which usually cause interfacial delamination. In this dissertation, an analytical model for thermo-mechanical stress analysis of multi-layered microelectronic structures has been developed and verified in the lab on actual BGA microelectronics packaging modules with Moiré interferometry technique. This analytical model, which is based on classic plate theory, considers each layer as a beam-type plate with orthotropic material properties. Compared to most other analytical models, the boundary conditions of this model can describe all the physical natures of the restraints. In this dissertation, we also investigated the influence of interfacial compliances on thermo-mechanical stresses for stiffer and softer adhesive layers.