Compact Low-Power Low-Noise Neural Recording Wireless Channel for High Density Neural Implants (HDNIs).

摘要

Biomedical implants hold the promise to restore functionality for patients who have been afflicted by debilitating diseases. The most successful of these technologies has been the cochlear implant that has restored hearing to thousands of patients around the world. However, progress in the field of neural recording devices has been slower, largely due to the vast differences in scale when it comes to recording. Recording from hundreds or even thousands of electrodes in the motion cortex is necessary for precise movement control in 3-dimension. The design of compact low-power circuits that allow for high-density neural recording is thus very crucial.;This thesis work presents the design, simulation and measurement results of various compact low-power circuit blocks necessary for high-density neural recording. These include a compact, low-power, low-noise frontend neural amplifier that utilizes current-feedback miller-compensation technique and occupies ∼0.0075 mm2 of silicon area while consuming < 1.35 muW of power from a 1.2V supply. The amplified analog signal is then digitized by a 2nd-order DeltaSigma analog-to-digital converter (ADC) that is based on a compact fully-differential self-biased amplifier. The core of the ADC consumes only 2.5muW from a 1.2V supply, when sampled at 1.6 MHz, thus achieving a 60.5fJ/conversion-step FOM and occupies 0.012mm2 of chip area.;This work also presents the design, simulation, and measurement results of an impulse-radio ultra-wideband (IR-UWB) transmitter with measured datarates up to 135Mbps with average power consumption ≈ 1.4 mW, and thus achieving a FOM ≈ 10pJ/bit. The transmitter's effective isotropic radiated power (EIRP) must fit within the mask defined by the Federal Communications Commission (FCC). Therefore, the oscillation frequency of the voltage-controlled oscillator (VCO), the pulse width, and the pulse amplitude are adjustable to ensure the transmitted pulse's power spectral density (PSD) fits within the FCC mask. The VCO's oscillation frequency is tuned through using an on-chip low-dropout (LDO) regulator that controls the VCO's supply voltage. Pulse-position modulation (PPM) was used as it is more noise immune compared to pulse amplitude modulation (PAM) and on-off keying (OOK). PPM also breaks the periodicity in the transmitted pulses, thereby reducing the discrete tones that can otherwise show up in the PSD and potentially violate the FCC mask.;Locking the oscillation frequency to the desired value is ensured through the use of a Phase Locked Loop (PLL) with Embedded Digital Tracking. The PLL's reference frequency can be the frequency used for wireless power harvesting. The PLL acquires lock within ≈ 1mus, and afterward the VCO starts operating in pulsed PPM mode. Once the PLL locks, most of its blocks are disabled to save power. The PLL occupies an area ≈ 0.2mm2 including the IR-UWB transmitter and the LDO regulator. Chip fabrication was in 0.13mum CMOS technology.