Performance issues in network on chip FIFO queues.

摘要

Increasing line rates require higher memory bandwidth and access speeds. With line rates expected to reach OC-12 (10 Gbps) values soon, memory bandwidth and access speeds are becoming a bottleneck in network performance. Memory cores in FIFO buffers frequently use Dual port SRAM or DRAM cores. We have looked at the performance related issues of these memory cores while proposing a 3-port DRAM cell to decrease the refresh rates and hence eventually allow for faster access times. This thesis also compares the different methods of addressing with respect to speed.