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Advanced materials and structures for nanoscale CMOS devices.

机译:用于纳米级CMOS器件的先进材料和结构。

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摘要

Technological innovations have accomplished the continued scaling of CMOS devices well into nanometer regime. Short channel effects have been suppressed by the use of thinner gate oxide, shallower junction depth, and sophisticated channel doping profile without changing its basic structure. However, further CMOS scaling will be much more intricate due to fundamental materials and process limitations. The advanced thin-body transistor structures can effectively suppress the short channel effects, separating the need of heavy channel doping and the state-of-the-art thin gate oxide. This dissertation investigates the integration of advanced materials in front-end processes with advanced thin-body transistor structures.; Two essential processes in molybdenum (Mo) metal gate technology are developed: damage-free sputtering and high-selectivity dry etching. The physical origin of Mo gate work function engineering is simultaneous modification of the microstructure and chemistry at the gate dielectric interface, as discussed in chapter 2.; The impact of gate process technology on hafnium oxide (HfO2) gate dielectric is explored. The increase in equivalent oxide thickness and leakage current is resulted from the generation of oxygen vacancy, which causes silicon interfacial layer formation and gate electrode Fermi-level pinning in MOS devices, as discussed in chapter 3.; Tunable work function Mo gate is demonstrated for adjusting threshold voltages of ultra-thin body MOSFETs for the first time. Integration of metal gate and high-k gate dielectric employing FinFETs is demonstrated for the first time; Mo-gated HfO2 CMOS FinFETs reduce gate leakage current over 3 orders-of-magnitude for inversion equivalent oxide thickness (1.72 nm) with comparable carrier mobility, as discussed in chapter 4.
机译:技术创新已经实现了将CMOS器件的持续按比例缩小到纳米级的要求。通过使用更薄的栅极氧化物,更浅的结深和更精细的沟道掺杂轮廓,可以在不改变其基本结构的情况下抑制短沟道效应。但是,由于基本材料和工艺限制,进一步的CMOS缩放将更加复杂。先进的薄体晶体管结构可以有效地抑制短沟道效应,从而消除了对重沟道掺杂和最新的薄栅极氧化物的需求。本文研究了先进材料在前端工艺中与先进的薄体晶体管结构的集成。开发了钼(Mo)金属栅极技术的两个基本工艺:无损伤溅射和高选择性干法蚀刻。 Mo栅极功函数工程的物理起源是同时修改栅极介电界面的微观结构和化学性质,如第二章所述。探索了栅极工艺技术对氧化ha(HfO2)栅极电介质的影响。等效氧化物厚度和漏电流的增加是由氧空位的产生引起的,氧空位导致了MOS器件中硅界面层的形成和栅电极费米能级钉扎;首次展示了可调整的功函数Mo gate用于调节超薄MOSFET的阈值电压。首次展示了使用FinFET的金属栅极和高k栅极电介质的集成; Mogated HfO2 CMOS FinFET可在具有相当的载流子迁移率的情况下将反型等效氧化物厚度(1.72 nm)降低到3个数量级以上,从而降低了栅极泄漏电流。

著录项

  • 作者

    Ha, Dae-Won.;

  • 作者单位

    University of California, Berkeley.;

  • 授予单位 University of California, Berkeley.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2004
  • 页码 152 p.
  • 总页数 152
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术 ;
  • 关键词

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