首页> 外文学位 >Injection locking based ultra low power radio frequency integrated circuits.
【24h】

Injection locking based ultra low power radio frequency integrated circuits.

机译:基于注入锁定的超低功率射频集成电路。

获取原文
获取原文并翻译 | 示例

摘要

Recent advances in radio frequency integrated circuit (RFIC) technology enable various innovative and versatile applications through ultra-low-power wireless link such as mesh sensor network, personal area network (PAN) and semi-active RFID. This thesis introduces energy efficient demodulator and transceiver design for wireless communications.;At the receiver front end, an ultra-low-power BPSK demodulator based on injection locked oscillators (ILOs) is introduced. Two second harmonic ILOs are employed to convert BPSK signals to ASK signals, which are then demodulated by an envelope detector to baseband. For sub-GHz applications, the ILOs are implemented using ring oscillators to allow compact chip area and ultra-low power dissipation. Bit error rate (BER) analysis of this demodulator indicates erroneous polarity flipping of demodulated bits due to phase noise of the ILO. The prototype chip is fabricated in a 65nm CMOS technology that consumes 228μW of power and occupies 0.014mm2 of die area. Measurement results reveal the demodulation of 750MHz 5Mb/s differential BPSK signal with a sensitivity of -43dBm. Theoretical BER analysis has been verified with erroneous flipping observed in the measurement and its probability close to the prediction.;Then, an innovative injecting locking based transceiver architecture for ultra low power operation is proposed. It applied the ILO based BPSK demodulator at the receiver side. The oscillating signal at one receiver ILO also injects to another transmitter ILO for accurate carrier generation. Thus local frequency synthesis circuit which consumes considerable portion of power in traditional transceiver is not required. This design is implemented in a 45nm CMOS SOI technology. Measurement results indicate that the transceiver achieves downlink demodulation of -35dBm BPSK signal at 5Mb/s data rate and uplink transmission of -23dBm ASK signal at 1Mb/s data rate with 0.93mA current consumption from 1V power supply.
机译:射频集成电路(RFIC)技术的最新进展通过超低功耗无线链路(例如网状传感器网络,个人区域网(PAN)和半主动RFID)实现了各种创新且用途广泛的应用。本文介绍了用于无线通信的高能效解调器和收发器设计。在接收器前端,介绍了一种基于注入锁定振荡器(ILO)的超低功耗BPSK解调器。采用两个二次谐波ILO将BPSK信号转换为ASK信号,然后将其由包络检波器解调为基带。对于低于GHz的应用,使用环形振荡器实现ILO,以实现紧凑的芯片面积和超低功耗。此解调器的误码率(BER)分析表明,由于ILO的相位噪声,导致解调后的比特的极性反转错误。原型芯片采用65nm CMOS技术制造,消耗228μW的功率,并占用0.014mm2的管芯面积。测量结果显示了对750MHz 5Mb / s差分BPSK信号的解调,灵敏度为-43dBm。理论上的误码率分析已经通过测量中观察到的错误翻转和接近预期的概率进行了验证。然后,提出了一种创新的基于注入锁定的收发器架构,用于超低功耗操作。它在接收机侧应用了基于ILO的BPSK解调器。一个接收器ILO上的振荡信号也注入另一个发射器ILO中,以产生准确的载波。因此,不需要在传统收发器中消耗相当一部分功率的本地频率合成电路。此设计采用45nm CMOS SOI技术实现。测量结果表明,该收发器以5Mb / s的数据速率实现了-35dBm BPSK信号的下行链路解调和以1Mb / s的数据速率实现了-23dBm ASK信号的上行链路传输,并且从1V电源消耗了0.93mA的电流。

著录项

  • 作者

    Zhu, Qiang.;

  • 作者单位

    Illinois Institute of Technology.;

  • 授予单位 Illinois Institute of Technology.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2012
  • 页码 95 p.
  • 总页数 95
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号