Auction algorithms have been applied in various linear network problems, such as assignment, transportation, max-flow and shortest path problem. The inherent parallel characteristics of these algorithms are well suited for Field-Programmable Gate Array (FPGA) hardware implementation. In this work, we focus on the acceleration of auction algorithms to solve the assignment problem.;The main contribution is to set up a flexible platform to generate efficient and extensible application-based hardware acceleration platform. It aims at solving both symmetric and asymmetric assignment problem. Our experimental results show that a 10X speedup can be achieved using 128 Processing Elements for a problem size of 500.
展开▼
