A second generation GENEric SYstems Simulator (GENESYS) for a gigascale system-on-a-chip (SoC).

摘要

Future opportunities for gigascale integration will be governed by a hierarchy of theoretical and practical limits that can be codified as follows: fundamental, material, device, circuit, and system. The exponential increase in on-chip integration is driving System-on-a-Chip (SoC) methodologies as a dominant solution for gigascale ICs. Therefore, a second generation generic systems simulator (GENESYS 2K4) is developed to address a need for rapid assessment of system performance metrics for billion-transistor systems-on-a-chip while maintaining the depth of core modeling codified in the hierarchy of limits. A newly developed system methodology incorporates a hierarchical block-based model, a dual interconnect distribution, a generic on-chip bus model, and cell placement algorithms. A comparison of simulation results for five commercial chip implementations shows increased accuracy in projecting die size, clock frequency, and power dissipation. ITRS projections for future technology requirements are applied with results indicating that increasing static power dissipation is a key impediment to continued advances in chip performance. Additionally, simulations of a generic chip multi-processor architecture utilizing several interconnect schemes shows that the most promising candidate for the future of on-chip global interconnect networks will be hierarchical bus structures providing a high degree of connectivity while maintaining high operating frequencies.