In contemporary society hand held devices have certainly become more prevalent in our daily lives. Smaller Chip Scale Packages are being developed with the purpose of meeting industry requirements. Due to this reduction in size Portable Electronic Devices (PED) are mishandled with greater frequency, which ultimately results an increase of drop impacts. Repetitive drops of PEDs eventually cause cracks in the solder joints that connect the IC with the PCB (Hunt 2005). This leads to the malfunction of the device. Taking this into consideration, the study of joint solder reliability impact is influenced. Computer aided Finite Element Analysis assists in the research and development of more efficient electronic packages that are ultimately more reliable.;In this thesis modified JEDEC board designs are studied. Additionally, square boards with different component configurations, sizes, and boundary conditions are proposed. Using ANSYS(2007), new boards are modeled and simulated. Newly designed boards are compared with JEDEC board on various levels. Initially, a parametric study of bare boards is conducted in order to prove that an excellent agreement between the bare board analysis and the actual component performance for the current JESDEC board drop test is obtainable. Next, multiple boards that contain a single component in their centers are examined. Finally, multiple boards that contain four components are studied and stress-strain relationship is reviewed. It was found that JESD22-B111 standard board causes the highest strain value and hence has the highest failure rate; yet, 5inch boards can reach similar values.
展开▼
