With the rapidly growing number of electronic appliances, embedded systems are becoming ubiquitous and omnipresent. Advances in semiconductor fabrication technology, stringent and sometimes conflicting design goals, and diminishing design turn-around times, impose heavy burdens on embedded system designers. Electronic design automation (EDA), which frees the designers from concentrating on the details, is thus becoming not only a useful supplement, but also an indispensable tool for the designers.; It is already known that application specific instruction-set processors (ASIPs) can achieve a good balance between efficiency and flexibility. In this dissertation, we present design methodologies, in the context of extensible processors, for custom instruction synthesis. We demonstrate the need for such methodologies by illustrating the size and complexity of the custom instruction design space. We propose cost functions to estimate the performance improvement for the custom instructions efficiently. We utilize static and dynamic pruning techniques to reduce the design space. The selected custom instructions are not constrained by the architectural parameters set a priori. For complex real-life applications, we take advantage of the hierarchical structure of the application program by first searching for custom instructions in leaf functions and sub-programs, and finally merging them into a solution for the entire application, which improves the scalability of the methodologies. Instead of considering each custom instruction separately and atomically, we take into account the impact of adding and dropping operations from each custom instruction on the entire instruction set, resulting in a more flexible and fine-grained approach. Experimental results indicate that our methodologies can significantly improve the performance and energy of the target processor, while keeping the design turnaround times short.; Incorporating custom instructions in a processor, although providing the means to performance improvement at a fine-grained level, may still not be sufficient for some real-time applications. On the other hand, the utilization of multiprocessors and co-processors in system design as coarse-grained hardware accelerators has already been studied in the hardware-software co-design area. However, no work has been performed on providing a unified synthesis methodology to combine the fine- and coarse-grained hardware accelerators. We provide a multi-level synthesis methodology to synergistically synthesize the custom instructions with multiprocessors. (Abstract shortened by UMI.)
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