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Design and implementation of ultra-low power pattern and sequence decoders.

机译:超低功耗模式和序列解码器的设计与实现。

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A key challenge in embedding pattern recognition intelligence onto ubiquitous sensing and communication interfaces in wireless integrated systems is to balance requirements on precision, complexity and power consumption in VLSI implementation. This dissertation investigates architectures for adaptive pattern recognition and sequence decoding, derived from statistical learning theory and Bayesian belief propagation on graphs, that lend naturally to efficient implementation in analog VLSI. Theoretical research in this area has resulted in forward decoding kernel machines (FDKM), a maximum a posteriori (MAP) based sequence decoder and has demonstrated state-of-art performance on various signal processing tasks in speech recognition and communications. The performance of FDKM depends on the discriminatory ability of an embedded large margin classifier. Investigation in this area has led to development of Gini-support vector machines, a sparse large margin classifier generating normalized output scores. These have been used extensively for image classification and voting networks. GiniSVM and FDKM systems have been optimized for accuracy and power dissipation and their architecture have been mapped onto a current-mode CMOS implementation. Non-volatile floating-gate MOS storage provides full analog programmability and trainability throughout all stages of the architecture. A calibration scheme, coupled with a chip-in-the-loop retraining procedure, cancels imprecision due to fabrication-induced mismatch in the analog circuit implementation. Calibration and retraining of a 3mm x 3mm SVM/FDKM chip fabricated in 0.5um CMOS technology, programmed for a speaker verification task, yields real-time recognition accuracy on par with floating-point software while dissipating sub-microwatt power. Applications include power-efficient smart sensors, implantable biomedical monitoring, biometric verification, human-computer interfaces, and adaptive iterative decoding communication systems.
机译:在无线集成系统中将模式识别智能嵌入到无处不在的传感和通信接口上的一个关键挑战是平衡VLSI实现中对精度,复杂性和功耗的要求。本文从统计学习理论和图上的贝叶斯信念传播出发,研究了自适应模式识别和序列解码的架构,这些架构自然地有助于在模拟超大规模集成电路中的有效实现。在这一领域的理论研究导致了前向解码内核机器(FDKM),基于最大后验(MAP)的序列解码器,并展示了语音识别和通信中各种信号处理任务的最新性能。 FDKM的性能取决于嵌入式大余量分类器的区分能力。在这一领域的研究导致了Gini支持向量机的发展,Gini支持向量机是一种稀疏的大余量分类器,用于生成标准化的输出分数。这些已广泛用于图像分类和投票网络。 GiniSVM和FDKM系统已针对精度和功耗进行了优化,其架构已映射到电流模式CMOS实现中。非易失性浮栅MOS存储在架构的所有阶段都提供了完整的模拟可编程性和可训练性。校准方案,再加上芯片在环再训练程序,消除了由于模拟电路实现中制造引起的失配而引起的不精确性。对以0.5um CMOS技术制造的3mm x 3mm SVM / FDKM芯片进行校准和再培训,针对扬声器验证任务进行了编程,可提供与浮点软件同等的实时识别精度,同时消耗亚微瓦功率。应用包括省电智能传感器,可植入生物医学监测,生物特征验证,人机界面以及自适应迭代解码通信系统。

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