Many high-radix Network-on-Chip (NOC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe high-radix Clos Network-on-Chip (CNOC) is the most promising with its low average hop counts and good load-balancing characteristics. In this dissertation, we present three different CNOC architectures - the buffered electronic CNOC, the BufferLess phOtonic ClOs Network-on-chip (BLOCON), and the bufferless electronic CNOC - with high throughputs, high power efficiencies, and low zero-load latencies.;For the buffered electronic CNOC, we propose (1) a high-radix router architecture with Virtual Output Queue (VOQ) buffer structure and Packet Mode Dual Round-Robin Matching (PDRRM) scheduling algorithm to achieve high speed and high throughput in the buffered CNOC, (2) the design of Hierarchical Round-Robin Arbiter (HRRA) for high-radix high-speed NOC routers, (3) a heuristic floor-planning algorithm to minimize the power consumption caused by the long wires. We compare the delay, power, and area performance of the 64-node buffered CNOC with other NOC topologies under various synthetic traffic patterns and SPLASH-2 benchmark traces in the simulation results.;For BLOCON that exploits silicon photonics, we propose (1) a scheduling algorithm named Sustained and Informed Dual Round-Robin Matching (SIDRRM) to solve the output contention problem, (2) a path allocation scheme named Distributed and Informed Path Allocation (DIPA) to solve the Clos network routing problem, and (3) a methodology to achieve an optimal off-chip laser-power budget. In the simulation results, we show that with SIDRRM and DIPA, BLOCON improves the delay and on-chip power performance of the compared electrical and photonic NOC architectures over synthetic traffic patterns and SPLASH-2 traces.;For the bufferless electronic CNOC, we propose an architecture that avoids the traditional methods such as packet deflecting and dropping applied in the traditional electronic bufferless NOCs. Our proposed architecture arranges the routes and departure times for packets in the control plane before transmitting the packets in the data plane, to achieve high throughput and low-power consumption. We propose (1) a novel scheduling scheme, called Router Matching First (RMF) with low control-plane overhead and high throughput to solve the output contention and Clos network routing problems, and (2) a router placement methodology for the 64x64 bufferless electronic CNOC to minimize the total length of the data-plane interconnects. The experimental results show that with a moderate area overhead, the 64x64 bufferless Clos NOC consumes only 1.43W static power and achieves at least 72% throughput under the tested synthetic traffic patterns.
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