Design of a residential gateway core for a SONET over DWDM broadband access network.

摘要

The residential gateway (RG) is an intelligent switching device connected to the SONET over DWDM broadband access network for providing symmetric bidirectional multiservices to home users. Each RG consists of the RG core and the RG interface with Ethernet, video, audio, telephone and other home applications.; This thesis presents the RG core design based on Xilinx Virtex-II FPGA technology. To meet the challenge of multi-clock processing, a new approach called "zero-address transaction," is adopted.; The functionality and feasibility of the design are verified by the results of simulation at different levels of accuracy.