A hardware implementation of low-density parity-check coding for the Digital Video Broadcast-Satellite Version 2 standard.

摘要

We propose a hardware implementation of low-density parity-check (LDPC) codes to satisfy the Digital Video Broadcast-Satellite Version 2 (DVB-S2) standard. We examine the current literature and prior work. The LDPC decoding algorithm is briefly introduced with both probability and log-likelihood formulations of the algorithm. The DVB-S2 standard is also introduced and the particular requirements of the LDPC decoding module are discussed.; We introduce several hardware architecture considerations for DVB-S2 LDPC decoding. Our hardware design is presented, including state diagram, pipeline diagram, block diagram, and explanations of all elements of each diagram.; A final chapter discusses parallelization issues and techniques for our design.