Computation of the cross ambiguity function using perfect reconstruction DFT filter banks.

摘要

This dissertation presents a novel method for computing the Cross Ambiguity Function (CAF) using over-sampled and maximally decimated perfect reconstruction Discrete Fourier Transform Filter Banks (DFT FBs). As with the maximally decimated filter banks, the over sampled filter banks can be used to efficiently filter the signals into sub-bands, calculate the CAF in each sub-band, and then coherently reconstruct the CAFs, provided the DFT Filter Bank's prototype filter meets specific constraints. In this manner, the Time Difference of Arrival (TDOA) accuracy is improved over non-coherent reconstruction, while the Frequency Difference of Arrival (FDOA) accuracy is maintained. One advantage is that, if there is interference from Narrow-Band (NB) signals, the interference can be removed prior to reconstruction of the CAF.; Maximally decimated filter banks are more computationally efficient than the over-sampled filter banks, but they suffer from the fact that there is a limited choice for the prototype filter, with poor side-lobe properties. The over-sampled filter banks are somewhat more computationally complex, but prototype filters with better side-lobe characteristics can be developed. This allows the narrow band interference to be removed more efficiently, since interfering signal's energy is concentrated in a smaller number of sub-bands. The design constraints for the prototype filter for the over-sampled filter bank are the same as that of the cosine modulated filter bank.; The probability of detection performance for the CAF is derived as a function of the probability of false alarm, effective input SNR and number of independent input samples. The distribution is shown to be Rician, so the probability of detection can be computed by calculating the Marcum Q function.; Since computing the CAF is very computationally intensive, and can take a significant amount of time to process on a General Purpose Processor, the CAF algorithms have been implemented in a Field Programmable Gate Array (FPGA) for a significant performance increase.