Hardware implementation of a packet switch with an optical core.

摘要

With the rapid development of optical communications, transport of data over fiber channel can now reach rates as high as Gigabits per second. In order to take advantage of this tremendous bandwidth, fast packet switches that can operate at the same bit rates must be developed; as these modules currently represent the bottleneck of high speed telecommunication networks.;This thesis will present a scaled down demonstrator version of the packet switch, implemented on programmable logic devices (Stratix FPGA by Altera Corp.) forming electronic "islands" that are interconnected by a reconfigurable central stage crossbar. The FBP algorithm was implemented using VHDL at RTL level of abstraction. The design has 8 inputs ports, 8 output ports and 2 sectors in each buffering stage. Communication among modules within the demonstrator is performed through a custom high speed 10 Mbps interface. We will present our implementation of the central stage using first an electronic crossbar switch and then an optical switch (a Wavelength Selective Switch by Metconnex Inc.). Finally, we will also describe our configurable FPGA-based traffic generator built using the Nios II development board, Stratix Edition. The generator consists of a Hardware packet generator, a Nios II processor playing the role of the "Maestro", and a custom graphical user interface to provide a friendly way to set traffic parameters. Our traffic generator is capable of supplying the switch under test with 2 different traffic models: Self Similar and Markov Modulated Bernoulli Process.;Keywords. Optical Networks, Packet Switching, Field Programmable Gate Array (FPGA), Very High Speed Integrated Circuit Hardware Description Language (VHDL), Traffic Generation;An optoelectronic packet switch architecture using reconfigurable optics in the central stage will be described. The central stage is surrounded by two electronic buffering stages partitioned into sectors to ease memory contention and to limit the size of the memory required for each sector. A Flexible Bandwidth Provision algorithm (FBP), is used to change the configuration of the central stage; essentially creating various numbers of internal paths that allocate variable bandwidth between sector pairs depending on traffic demands.