In the recent years, signal integrity has been at the forefront of new developments in CAD algorithms focussed on high-speed electronic circuits. With the continuous rise in operating frequencies, the interconnect effects such as delay, distortion, crosstalk and ringing become the dominant factors limiting the performance of VLSI systems. At relatively higher frequencies and increased level of integration, it is not always possible to find analytical or simulatable models for high-speed modules such as packages, vias, connectors, nonuniform transmission lines etc. In such a scenario, these devices are characterized by tabulated multiport parameters (S, Y, Z or T), obtained either through measurements or from the physical layout using rigorous full-wave electromagnetic simulations. However, transient simulation of such frequency-dependent tabulated data in the presence of nonlinear devices to obtain a global electrical assessment is a CPU expensive process due to the mixed frequency/time problem. Recently, several macromodeling algorithms have been proposed for this purpose. However, a major difficulty associated with these algorithms is that, they are either not able to guarantee the passivity of the resulting macromodel or when guaranteeing the passivity, they become prohibitively CPU expensive. In addition, further challenges are posed by modern designs which tend to contain multiple diverse high-speed modules. Such an emerging scenario typically leads to large sized circuit matrices and warrants unified passive reduction algorithms to facilitate fast simulations. However, the currently available algorithms cannot perform global passive reduction of such an environment with multiple diverse high-speed modules.;In this thesis, novel algorithms are presented to address the above issues. A systematic methodology is presented for the passive macromodeling of tabulated data networks. For this purpose, fast passivity verification and enforcement algorithms are presented. These algorithms are suitable for small as well as large sized macromodels of tabulated networks. In addition, an algorithm with a guaranteed search direction is presented, to reduce the number of iterations during the passivity enforcement process. Also, a new algorithm is presented for a global reduction of circuits containing diverse high-speed modules. This algorithm permits a novel formulation to guarantee the passivity of the resulting reduced-order model. Also, an efficient algorithm is presented for the second-level reduction, to obtain further compact macromodels. The developed algorithms are robust and practical, and suitable for implementation in state-of-the-art design automation tools.
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