Time-interleaved DeltaSigma-DAC for broadband wireless applications.

摘要

The analysis and design of a time-interleaved delta-sigma digital-to-analog converter (TIM DeltaSigma-DAC) is presented. The digital front-end of the TIM DeltaSigma-DAC comprises a 95th-order time-interleaved-by-8 FIR interpolation filter and a 3rd-order time-interleaved-by-8 DeltaSigma modulator. The time-interleaved architecture uses parallelism to support a low OSR of 8, which results in a large effective bandwidth for broadband applications. The 4-bit output of the DeltaSigma modulator is converted into analog using 16 current-steering cells with continuous current calibration. The chip was fabricated in 90nm CMOS. It was designed to operate at 4GS/s with a bandwidth of 250MHz. The analog back-end was tested with modulated data from a simulation of the digital front-end. It was measured at 2.66GS/s and achieved a bandwidth of 166MHz, an SNR of 46dB and an SFDR of 56dB. At 2GS/s, the prototype consumed 102mW from a 1V supply.