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High Speed ADC Design Methodology.

机译:高速ADC设计方法论。

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摘要

Analog-to-digital converter (ADC) is a very fundamental and key part to nearly all kinds of electronics. The applications cover a wide range requiring different resolution to different sampling rate, including UWB systems, radar detection, wide band radio receivers, optical communication links, CCD imaging, ultrasonic medical imaging, digital receivers, base stations, digital video (for example, HDTV), xDSL, cable modems, and fast Ethernet. Among them, lower resolution very high speed ADC is a critical part for building UWB system, disk drive read channels and optical communication.;This thesis consists of two parts. The first part focuses on the design of a high speed low resolution flash ADC in 90nm technology. Capacitive interpolation technique was used in this flash ADC in order to reduce the hardware requirement and input capacitance. No sample-and-hold (S/H) circuit is needed since the distributed capacitors (including capacitors in the very front end and the interpolated capacitors) serve to sample and hold the signals. Offset cancellation and averaging techniques are also implemented to reduce the offsets and the non-linearity. The ADC design achieves a sampling speed of 2.3GSps with 4 bits resolution in 90nm CMOS technology.;The second part describes a new comprehensive ADC design methodology for capacitive interpolated flash ADCs, aiming to provide a quantitative, yet handy design guideline for circuit designers to conduct practical ADC designs. This new ADC design methodology provides a quantitative and comprehensive mapping between ADC chip level performance specs and various design parameters at different levels, such as, interpolation factor, number of stages, pre-amplifier bandwidth, loading effects, transistor sizes, technology parameters and etc. It serves to allow IC designers to conduct quick and quantitative flash ADC designs for well-balanced overall chip performance in practices. A dynamic power consumption analysis technique for capacitive interpolated flash ADCs is also discussed.;Index terms: flash ADC, high speed, interpolation, design methodology, conversion rate, resolution, dynamic power dissipation.
机译:模数转换器(ADC)是几乎所有电子产品中非常重要的基础部分。这些应用涵盖了需要不同分辨率和不同采样率的广泛范围,包括UWB系统,雷达检测,宽带无线电接收器,光通信链路,CCD成像,超声医学成像,数字接收器,基站,数字视频(例如HDTV) ),xDSL,电缆调制解调器和快速以太网。其中,较低分辨率的超高速ADC是构建UWB系统,磁盘驱动器读取通道和光通信的关键部分。第一部分着重于90nm技术的高速低分辨率闪存ADC的设计。为了减少硬件要求和输入电容,在此闪存ADC中使用了电容插值技术。不需要采样保持(S / H)电路,因为分布式电容器(包括最前端的电容器和内插电容器)用于采样和保持信号。还实现了偏移消除和平均技术,以减少偏移和非线性。 ADC设计在90nm CMOS技术中以4位分辨率实现了2.3GSps的采样速度。第二部分介绍了一种针对电容内插式Flash ADC的新型综合ADC设计方法,旨在为电路设计人员提供量化但方便的设计指南进行实用的ADC设计。这种新的ADC设计方法提供了ADC芯片级性能规格与不同级别的各种设计参数之间的定量和全面映射,例如插值因子,级数,前置放大器带宽,负载效应,晶体管尺寸,技术参数等它使IC设计人员能够进行快速,定量的Flash ADC设计,以在实践中实现均衡的整体芯片性能。还讨论了一种用于电容插值闪存ADC的动态功耗分析技术。关键词:闪存ADC,高速,插值,设计方法,转换速率,分辨率,动态功耗。

著录项

  • 作者

    Tang, He.;

  • 作者单位

    University of California, Riverside.;

  • 授予单位 University of California, Riverside.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2010
  • 页码 147 p.
  • 总页数 147
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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