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Verification of large industrial circuits using SAT based reparameterization and automated abstraction-refinement.

机译:使用基于SAT的重新参数化和自动抽象提炼对大型工业电路进行验证。

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Automatic formal verification of large industrial circuits with thousands of latches is still a major challenge today due to the state space explosion problem. Moreover, BDD based algorithms are very sensitive to the variable ordering. Satisfiability (SAT) procedures have become much more powerful over the last few years, and hence they have been used in formal verification of large circuits with techniques like automated abstraction refinement and ATPG.; This thesis addresses the capacity challenge at multiple levels. First, at the core, I provide new algorithms for both BDD based and SAT based image computation. Image computation involves efficient quantification of variables from Boolean functions. I propose BDD based algorithms that use various combinatorial optimization techniques to obtain better quantification schedules, and in the later part, consider novel non-linear quantification schedules. The SAT based image computation uses algorithms for efficiently enumerating satisfying assignments to a Boolean formula, and for storing the enumerated assignments. Building upon this enumeration algorithm, I propose a novel SAT based reparameterization algorithm that increases the capacity of symbolic simulation by large extent. The reparameterization algorithm recomputes a much smaller representation for the set of states, whenever the size of the representation of state set becomes too large in symbolic simulation. These improvements help in bounded model checking of large systems, by allowing for much deeper depths. I demonstrate a 3x improvement in the runtime and space requirement over existing BMC algorithm and BDD based symbolic simulator on large industrial circuits. Finally, the reparameterization algorithm is incorporated in a SAT based automated abstraction-refinement framework. The reparamaterization algorithm can simulate much longer abstract counterexamples than previously possible. I then extract the refinement information from the simulation, completing the abstraction-refinement loop. Thus, contributions beginning at the core problem of image computation, through state space travesals and continuing all the way up to the abstraction-refinement are addressed in this thesis.
机译:由于状态空间爆炸问题,具有数千个闩锁的大型工业电路的自动形式验证仍然是当今的主要挑战。此外,基于BDD的算法对变量排序非常敏感。可满足性(SAT)程序在过去几年中变得越来越强大,因此已通过自动抽象优化和ATPG等技术用于大型电路的形式验证。本文从多个层面解决了容量挑战。首先,在核心部分,我为基于BDD和基于SAT的图像计算提供了新的算法。图像计算涉及对布尔函数变量的有效量化。我提出了基于BDD的算法,该算法使用各种组合优化技术来获得更好的量化进度表,在后面的部分中,将考虑新颖的非线性量化进度表。基于SAT的图像计算使用算法来有效枚举对布尔公式的满意分配,并存储所枚举的分配。在此枚举算法的基础上,我提出了一种新颖的基于SAT的重新参数化算法,该算法在很大程度上提高了符号仿真的能力。每当在符号仿真中状态集表示的大小变得太大时,重新参数化算法都会为状态集重新计算更小的表示。这些改进允许更深的深度,从而有助于大型系统的有界模型检查。我证明了在大型工业电路上,与现有的BMC算法和基于BDD的符号模拟器相比,运行时间和空间要求提高了3倍。最后,将重新参数化算法并入基于SAT的自动抽象提炼框架中。重新参数化算法可以模拟比以前更长的抽象反例。然后,我从仿真中提取优化信息,从而完成了抽象-优化循环。因此,本文致力于解决从图像计算的核心问题开始,通过状态空间遍历,一直持续到抽象提炼的过程。

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