Design, modeling, and analysis of networks-on-chip for systems-on-chip .

摘要

Systems-on-Chip (SoCs) are attractive platforms for embedded computing, because integrating a system or a complex subsystem on a single chip provides better performance, reliability, and cost per function. The performance of an SoC is decided not only by the performance of functional units composing it but also by the efficiency with which these functional units communicate. It is the SoC's communication architecture which decides the cooperation efficiency. As the complexity of SoCs increases, on-chip communication cost also increases, and low power management requires more flexible communication schemes. Furthermore, over each technology generation, while shrinking feature sizes reduce gate delays exponentially, global wire delays increase exponentially at the same time. This work studies the communication subsystems of SoCs and their codesign with computation and memory subsystems. First, we proposed a novel on-chip communication architecture, the Application-Specific Network-on-Chip (ASNoC). ASNoCs achieve higher performance and lower cost than regular-topology Networks-on-Chip (NoCs) by using hierarchies, irregular topologies, floorplan estimation, and selected protocols. We proposed a systematic ASNoC design methodologies, compatible with current hardware/software codesign flows. Using the methodology, we designed ASNoCs for two SoCs. Results show that the ASNoCs offer significantly higher performance and lower cost than regular-topology NoCs. Second, we proposed a general design methodology for on-chip communication architectures. Our methodology formalizes on-chip communication architecture designs; it can design, model, and analyze all types of on-chip communication architectures. Different communication architectures can be designed at the same time and evaluated based on the same standard. Using this methodology, we designed and compared bus-based and crossbar-based architectures for an SoC in the 130 nm technology. Third, we proposed a novel on-chip interconnection structure, called wave-pipelined interconnection. Wave-pipelined interconnection is pipelined without using latches. It uses less power and delivers a much higher throughput. It is suitable for globally asynchronous and locally synchronous clock schemes. In the 70 nm technology, wave-pipelined interconnection achieves 10 GHz and an 80 Gbps throughput, and eliminates 88% of delay variations caused by crosstalk noise.