Scalable moduli multiplier designs for cryptographic applications folded in FPGAs.

摘要

High secure cryptographic systems require large bit-length operands which presents a challenge to their efficient hardware implementation especially in embedded devices. Modular multiplication, which is normal multiplication modulo some integer, is the core operation in well known cryptosystems like RSA and Elliptic Curve (ECC). Therefore, it is important to employ efficient multiplication techniques to improve the overall performance of the cryptographic system. The ability to modify key lengths, for security reasons, suggests adaptability in multiplication bit-length. However, reconfigurability of multiplication is a difficult task, especially when bit-lengths are large, say over 500 bits. For fixed bit-lengths, much work has been done in the range of 32, 64 or even 128 bits for advanced microprocessors and DSPs. The objective of this work is to design large adaptable bit-length multipliers that can be employed in cryptographic systems. We present a multiplication scheme for higher radix multiplexer-based array multipliers and we suggest a parallelization of the scheme within a single FPGA based implementation. We, also, present a modular multiplier; that employs the higher radix multiplexer-based array multipliers to perform the multiplication operation, based on the ordinary Montgomery's multiplication algorithm.