Controlling activation energy to wafers and walls in plasma processing reactors for microelectronics fabrication.

摘要

The trend to shrink modern microelectronic devices is pushing processing technologies to unprecedented limits. In particular, plasma processing should meet the stringent requirements of developing features at future technological nodes. Microprocessors now available have oxide layers in gate stacks which are only a few mono-layers (1-2 nm) thick. Therefore at future technology nodes even a monolayer deviation can have significant implications on performance. In this work, relevance of low pressure, high plasma density discharges for advanced semiconductor processing in the fabrication of fine features in microelectronics are discussed.To meet the stringent requirements, plasma processing requires unprecedented control of the properties of reactive species onto the wafer (small scale) and walls of reactors (large scale). Ultimately, extreme control over the uniformity, composition, and energy of reactants is required as these are the enablers to processing delivering the requisite activation energy to various processing steps such as etching, deposition, etc. Different methods of controlling activation energy are investigated to achieve the fine balance between the uniformity, composition and energy of the reactants.Pulsed plasma ion implantation, a technique to form ultra-shallow junctions, is an important technology to enable advances in microelectronics industry. The characteristics of the ion energy and angular distributions (IEADs) incident onto the wafer are critical to determination of the junction properties. In particular, angular asymmetry in the IEADs was observed as a result of the curvature in the sheath edge. By changing the source design, the sheath symmetry was restored thereby making the IEADs angularly symmetric. Characterizing the IEADs enables improvement in the uniformity, repeatability and reliability of the implantation process.Extreme control in etching process technologies is critical to etch node feature geometries with high aspect ratios. Typical reactive ions based etching techniques is prone to issues such as microloading and mask charging thus limiting the precise control that can be achieved. Plasma atomic layer etching is therefore suggested to allow for precise atomic scale controllability. Precise control over IEADs incident onto the wafer enables extreme control in etching characteristics of the process. However, to keep integration costs low, it is important to utilize conventional plasma equipment while enabling such control. Recipes utilizing PALE processes have been investigated in conventional plasma sources for different gas mixtures to etch feature geometries of interest at future technological nodes. We found that, while feasible, PALE processes are slow compared to conventional etching. Recipes based on non-sinusoidal bias waveforms were investigated which, though increase the throughput, are still slow.Wafer-to-wafer reproducibility during plasma etching presents another challenge. The use of low-pressure, high-density discharges results in increasing buildup of etch products in the plasma reactor resulting in increased interactions of etch products with wafer and non-wafer surfaces, alike. Consequences of such interactions have been investigated for Ar/Cl2 inductively-coupled plasma etching of poly-Si. The interactions of etch products with the wafer ultimately results in decrease in etch rates while the chamber seasons due to interactions with the non-wafer surfaces. A proportional controller using bias voltage as an actuator and etch rate as the sensor was implemented to achieve real-time, closed-loop control of etch rate to counter the effects of seasoning.