首页> 外文学位 >High-Quality Test and Diagnosis for Small-Delay Defects.
【24h】

High-Quality Test and Diagnosis for Small-Delay Defects.

机译:小延迟缺陷的高质量测试和诊断。

获取原文
获取原文并翻译 | 示例

摘要

The scaling of fabrication technology not only provides us higher integration and enhanced performance in the design, but also the increased manufacturing defects. As a result, the stuck-at fault test alone cannot guarantee high test quality and in-field reliability. At-speed delay test using transition delay fault (TDF) model has been widely used in industry to detect the timing-related defects. The small-delay defect (SDD) is one type of such timing defects, which can be introduced by imperfect manufacturing process as well as pattern-induced on-chip noises, e.g., power supply noise (PSN) and crosstalk, causing chip failures by introducing extra delay to the design. As technology scales to 45nm and below, testing for SDDs is necessary to ensure the quality and reliability of high-performance integrated circuits.;The traditional at-speed test methods cannot ensure high test coverage of SDDs with a reasonable pattern count. As a result of semiconductor industry demand, commercial timing-aware automatic test pattern generation (ATPG) tools have been developed for SDD detection. However, these ATPG tools suffer from large pattern count and CPU runtime. Furthermore, none of these methodologies take into account the impact of design parameter variations and on-chip noises, e.g., process variations, PSN and crosstalk, which are potential sources of SDDs. Furthermore, it is vital to diagnose the SDD failures and show which are the major causes of the chip failures.;In this research, we propose new techniques and methodologies to improve the overall test quality of SDDs with a very small pattern set. From the implementation of the proposed procedures on both academic and industry circuits, our methods can result in a pattern count as low as a traditional 1-detect pattern set and long path sensitization and SDD detection similar or even better than the n-detect or timing-aware pattern set. The important design parameters and pattern-induced noises such as process variations, PSN and crosstalk are taken into account in the proposed methodologies. The new diagnosis flow is also proposed to identify whether the failure is caused by PSN, or crosstalk, or a combination of them.
机译:制造技术的规模化不仅为我们提供了更高的设计集成度和增强的性能,而且还增加了制造缺陷。结果,仅卡在故障测试上不能保证高测试质量和现场可靠性。使用过渡延迟故障(TDF)模型的全速延迟测试已在工业中广泛用于检测与时序有关的缺陷。小延迟缺陷(SDD)是此类时序缺陷的一种,它可能由不完善的制造过程以及图案引起的芯片上噪声(例如电源噪声(PSN)和串扰)引入,从而导致芯片故障。给设计带来额外的延迟。随着技术扩展到45nm及以下,SDD的测试对于确保高性能集成电路的质量和可靠性是必要的。传统的全速测试方法无法确保以合理的图案数量对SDD进行高测试覆盖率。由于半导体行业的需求,已经开发了用于SDD检测的商业定时感知自动测试图生成(ATPG)工具。但是,这些ATPG工具具有大量的模式数量和CPU运行时间。此外,这些方法中没有一个考虑到设计参数变化和片上噪声(例如,工艺变化,PSN和串扰)的影响,这是SDD的潜在来源。此外,至关重要的是诊断SDD故障并显示出是导致芯片故障的主要原因。在这项研究中,我们提出了新的技术和方法,以非常小的模式集提高SDD的整体测试质量。通过在学术和工业电路上实施建议的程序,我们的方法可以产生与传统的1-检测模式集一样低的模式计数,并且长路径敏化和SDD检测比n-检测或定时更好甚至更好。感知模式集。在所提出的方法中考虑了重要的设计参数和图案引起的噪声,例如工艺变化,PSN和串扰。还提出了新的诊断流程,以识别故障是由PSN,串扰还是它们的组合引起的。

著录项

  • 作者

    Peng, Ke.;

  • 作者单位

    University of Connecticut.;

  • 授予单位 University of Connecticut.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2010
  • 页码 216 p.
  • 总页数 216
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号