Complexity scalable and robust motion estimation for video compression.

摘要

Thanks to the fast development of network technology, transmission of high quality multimedia data becomes essential. However, the growth of data transferring capability is not always matched with the growth of bandwidth, specifically for wireless mobile environment. This is why the multimedia compression is so important for information technology development. Due to this importance, multimedia compression standards such as JPEG [6] and JPEG2000 [11] for still image compression and ISO/IEC MPEG-1 [4], MPEG-2 [7], MPEG-4 [9], ITU-T H.261 [5], H.263 [8], H.263+ [10], and JVT H.264/MPEG-4 AVC [29] for video compression have been developed since the early 90's.; Video compression is achieved through computationally complex encoding operations. Among these, the motion estimation/compensation is most complex. The complexity and the memory requirement is further increased in the long-term memory motion compensation (LTMC,[79]) that significantly improves coding efficiency by utilizing multiple reference frames. Therefore, in this dissertation, we propose low complexity motion estimation algorithms which use information of previously encoded and multiresolution frames to speed up the search. The main novelty of our proposed work comes from defining search and complexity reduction techniques that are optimized for LTMC. Also, we propose an efficient memory management control technique to reduce the decoder memory requirement for LTMC. For this we design a novel greedy search algorithm which searches for a subset of reference frames that results in minimal performance degradation rather than checking all the combination of reference frames as the optimal solution does.; Also, we propose a novel system-level error tolerance scheme specifically targeted for multimedia compression algorithms. While current manufacturing process classifies fabricated systems into two classes, namely, perfect and imperfect, our proposed scheme employs categories which are based on acceptable/unacceptable performance degradation. By enabling the use of systems that would otherwise have been discarded we seek to increase the overall yield rate in the system fabrication process. To achieve this, we propose hardware testing algorithms that aim at determining if faults in a given chip produce acceptable performance degradation, and a technique that can cancel the effect of those among the acceptable faults that can be compensated.