Self-calibrating processor speed: A new feedback loop for dynamic voltage scaling control.

摘要

The benefit of dynamic voltage scaling (DVS) is related to how compute-bound a workload is. The more time a processor stalls, the more a workload can be slowed down without incurring a proportional performance loss. However, determining a measure of "compute-boundedness" is not trivial; this property has often been inferred from secondary effects, such as cache miss rates.;We have developed a new mechanism for extrapolating compute-boundedness from minute variations of processor speed. By adjusting the processor speed by just a small amount, and extrapolating from the difference in execution cycles, we can precisely estimate a workload's execution time at any processor speed.;Moreover, simulation results suggest that a frequency step can be considerably smaller than the hundreds of megahertz that is offered by the current DVS-enabled processors. In fact, by adjusting the processor speed by as little as tens of megahertz, we can accurately predict what would be the execution times if the speed were adjusted by several hundreds of megahertz. This leads to a lightweight approach to CPU clock scaling called the self-calibrating feedback loop: while a workoad is executing, adjust the processor speed by just a little to quickly assess how compute-bounded the workload is, then decide on the optimal processor speed.