片上多核处理器缓存子系统优化的研究

目录

声明

ABSTRACT

Acknowledgement

Contents

List of Tables

List of Figures

Algorithms

1 Introduction

1．1 Introduction to CMP Memory Subsystem

1．2 Background and Motivation

1．2．1 Dual-Partitioning Multicasting for On-Chip Networks

1．2．2 Exploiting STT-RAM for Low Power Cache Memory

1．2．3 Thread Progress Aware Coherence Adaption

1．3 Organization

2 Dual-Partitioning Multicasting for NoC

2．1 Introduction

2．2 Dual Partitioning Multicasting

2．2．1 Multicast Packets Categorization

2．2．2 Dual Partitioning Multicasting

2．2．3 Unicast Aware Mechanism

2．3 DPM Implementation

2．3．1 DPM Router Architecture

2．3．2 Deadlock Free Analysis

2．4 Experiments and Analysis

2．4．1 Simulation Methodology

2．4．2 Results and Analysis

2．5 Conclusion

3 Exploit STT-RAM for Low Power Cache Memory

3．1 Introduction

3．2 Related Work

3．2．1 Reducing STT—RAM write activities

3．2．2 Relaxing STT-RAM retention time

3．2．3 Refresh on Volatile Memory

3．3 Cache Coherence Enabled Adaptive Refresh

3．3．1 System Architecture

3．3．2 Cache Coherence Enabled Adaptive Refresh

3．4 Experiments and Analysis

3．4．1 Experimental Setup

3．4．2 Results and Analysis

3．5 Conclusion

4 Thread Progress Aware Coherence Adaption

4．1 Introduction

4．2 Problem Formulation

4．3 Thread ProgrEss Aware Coherence Adaption

4．3．1 Overview

4．3．2 Thread Progress Estimation

4．3．3 Thread Categorization

4．3．4 Coherence Adaption

4．4 Implementation

4．4．1 Integrating Hybrid Protocols

4．4．2 Implement TEACA

4．5 Experiments and Analysis

4．5．1 Evaluation Methodology

4．5．2 Overall Results

4．5．3 Sensitivity Analysis

4．6 Conclusion

5 Conclusion

Bibliography

A 论文概要

A．1 摘要

A．2 论文概要

A．2．1 片上多核处理器缓存子系统简介

A．2．2 本文的研究内容和贡献

List of Publications