首页> 外国专利> MULTI-CORE PROCESSOR, MULTI-CORE SYSTEM AND ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF SHARING CACHE IN MULTI-CORE PROCESSOR

MULTI-CORE PROCESSOR, MULTI-CORE SYSTEM AND ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF SHARING CACHE IN MULTI-CORE PROCESSOR

机译:多核处理器,包括其的多核系统和电子设备以及在多核处理器中共享缓存的方法

摘要

PURPOSE: A multi-core process, a multi-core system, an electronic device, and a cache sharing method of the multi-core process are provided to operate cores by sharing a command cache and effectively relay the collision of command request signals between the cores, thereby reducing the whole size and increasing an operation speed. CONSTITUTION: A command cache (200) stores commands. Cores (100-1~100-n) share the command cache. The cores successively perform the operations corresponding to the commands by receiving the commands corresponding to continuous addresses from the command cache. The cores include buffers (110-1~110-n) which execute the commands which are received from the command cache. The cores successively perform the operations corresponding to the commands stored in the buffers.
机译:目的:提供一种多核进程,多核系统,电子设备以及该多核进程的缓存共享方法,以通过共享命令缓存来操作核心,并有效地中继命令请求信号之间的冲突。芯,从而减小了整体尺寸并提高了操作速度。构成:命令高速缓存(200)存储命令。内核(100-1〜100-n)共享命令缓存。内核通过从命令高速缓存接收与连续地址相对应的命令来连续执行与命令相对应的操作。内核包括执行从命令高速缓存接收的命令的缓冲器(110-1〜110-n)。内核依次执行与存储在缓冲区中的命令相对应的操作。

著录项

  • 公开/公告号KR101356541B1

    专利类型

  • 公开/公告日2014-01-29

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20120002394

  • 发明设计人 박인철;김봉진;송진욱;

    申请日2012-01-09

  • 分类号G06F15/80;G06F9/46;

  • 国家 KR

  • 入库时间 2022-08-21 15:41:37

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