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FPGA Implementation of MIMO for Visible Light Communication

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英文摘要

目录

List of abbreviations

Chapter 1 Introduction

1.1 Background

1.2 Fundamentals of VLC

1.3 Research project

1.4 Thesis organization

Chapter 2 MIMO for Visible Light Communication

2.1 System model

2.2 Spatial multiplexing

2.3 Spatial diversity

2.4 Dual Diversity MIMOfor VLC

2.5 Summary

Chapter 3 Hardware development

3.1 System overview

3.2 Development

3.3 Singular Value Decomposition

3.4 CORDIC

3.5 Summary

Chapter 4 Pseudoinverse implementation in FPGA

4.1 Pseudoinverse of a 2x2 matrix

4.2 Pseudoinverse of a 4x4 matrix

4.3 Module integration

4.4 Design evaluation

4.5 Summary

Chapter 5

5.1 Summary

5.2 Future work

参考文献

致谢

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摘要

As theradiofrequency(RF)spectrum gets more and more congestedwith our constant use of Wi-Fi and 3G/4G,newer systems are being designed to alleviate if not replace some older ones. Visible Light Communication (VLC),a system in which information uses visible light as the media to transmit information has been showing promising results for indoor use. Combined with the technologies that are used in RF,it can provide high performance for relatively low costs. Techniques such as the orthogonalfrequencydivisionmultiplexing modulation andmultipleinputmultiple output (MIMO) can be adapted to work with visible light,they might not necessarily work without adjustment as the characteristics of RF waves and visible light waves differ.As part of a project to implement a VLC system on aFPGAhardware platform,the MIMOaspect is studied from a VLC point of view,which differs slightly from its RF counterpart.As the SNR is expected to be sufficiently high,azero-forcing decoder with ordered successive interference cancellation is implemented. To do so,the pseudoinverseof the channel matrix needs to be computed. This is acomplex process and can be done via different methods. We opt for the method using the singular value decomposition of a matrix to determine its pseudoinverse.Since resources available on hardware aremore restricted than with software,hardware-efficient algorithms are used toget the most of FPGAs.

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