文摘
英文文摘
声明
Chapter 1 Introduction
1.1 Digital Communication Systems
1.2 Error Control Coding
1.2.1 Types of Errors
1.2.2 Types of Codes
1.2.3 Error Control Strategies
1.3 Shannon Limit
1.4 Motivation and Outline of the Dissertation
Chapter 2 Linear Block Codes
2.1 Introduction to Linear Block Codes
2.1.1 Generator Matrix
2.1.2 Parity Check Matrix
2.2 Minimum Distance
2.3 Maximum-Likelihood Decoding
2.4 Cyclic Codes
2.5 Quasi-Cyclic Codes
Chapter 3 Low-Density Parity-Check Codes
3.1 Representations of LDPC Codes
3.1.1 Matrix Representation of LDPC Codes
3.1.2 Graphical Representation of LDPC Codes
3.2 Encoding of LDPC Codes
3.2.1 Systematic Encoding
3.2.2 Richardson's Efficient Encoding
3.3 Decoding of LDPC Codes
3.3.1 Majority-Logic Decoding
3.3.2 A Bit Flipping Algorithm
3.3.3 The Sum-Product Algorithm
3.4 Constructions of LDPC Codes
3.4.1 Constructions of Random LDPC codes
3.4.2 Constructions of Structured LDPC codes
Chapter 4 Cycles in LDPC Codes
4.1 Paths
4.2 Cycles
4.3 Cycle Effects on the Performance of LDPC Code
4.4 Determination of Minimal Matrices of Simple Cycles
Chapter 5 Cycles in Expanded LDPC Codes
5.1 Introduction
5.2 Expanded LDPC Codes
5.2.1 Permutation and Permutation Matrix
5.2.2 Expanded LDPC Codes
5.3 Cycle Relationships in Protograph LDPC Codes
5.4 Limitation of Lifting QC-LDPC Codes
5.4.1 Some Results of Lifting in QC-LDPC Codes
5.4.2 Limitation of QC-LDPC Codes
Chapter 6 Cycle Analysis of QC-LDPC Codes
6.1 Introduction
6.2 Necessary and Sufficient Conditions for the Existence of Balanced Cycles
6.3 Determination of Minimal Matrices of Balanced Cycles
6.4 Determination of the Shortest Balanced Cycles
Chapter 7 Conclusion and Future Work
7.1 Summary and Contributions
7.2 Future work
Appendix A
Bibfiography
Publications
Resume
Acknowledgements