MINIMIZATION OF AREA AND POWER OF OMOS OOMBINATIONAL CIRCUITS USING A MODIFIED SIMULATED ANNEALING TECHNIQUE

摘要

Transistan size, power consumption, and signal delay ane cnitical and conflicting criteria for optimal design of digital VLSI circuits. In this paper, a continuous-time simulated annealing algorithm is proposed to minimize the anea and power of OMOS combinational circuits with delay constraints. Minimization is carried out at the gate level with the abjective functions and constnaints denived from aircuit-level analysis. The algarithm has been implamented in a computer program and validated using classical minimization problems with known optima. A CMOS full adder and a decoden ane optimized using the proposed algorithm and results are presented.