System-on-Chip Implementation and Fault-Coverage Estimation of a Fault-Tolerant Finite State Machine

摘要

This paper presents a methodology for implementing fault tolerant finite state machines on System-on-Chip. The SoC recently appeared on the market permits a very efficient interaction between the microcontroller and the FPGA allowing a very efficient implementation of the fault detection and fault recovery strategy. Our work takes into account fault tolerance in the case combinatorial or sequential circuits. The general case of a finite state machine (FSM) is presented. The FSM mapped in hardware on the FPGA is complete of a checker that permits the identification of class of faults. When a fault is detected, an interrupt for the microcontroller is generated. The interrupt handling routine partially reprograms the FPGA to override the part of memory configuring the faulty block. The proposed methodology has been implemented on the recently presented Atmel AT94K FPSLIC SoC and a novel technique to validate the obtained results is introduced. This technique allows injecting faults in the FPGA exploiting the partial reconfiguration feature. The performance evaluation of the proposed methodology is carried out in terms of Mean Time to Repair (MTTR), Fault coverage and hardware complexity.