Modeling, simulation and synthesis: From Simulink to VHDL generated hardware

摘要

Today, many systems designers use software tools such as Matlab to model a complex, mixed-technology system prior to physically building and testing the system. These tools, along with their associated toolboxes provide an effective means for the initial modeling and simulation stages in a project. Such software tools also provide means to extract information in a relevant format to aid the physical realisation. This paper will describe the use of a toolbox that can analyze and process a Simulink block diagram model in order to produce a VHDL representation of the model. The derived VHDL model will consist of definitions mapped from the Simulink model. This approach may enable a user to develop and simulate a digital control algorithm using Matlab and once complete, convert this to VHDL code. This would then be synthesized into digital logic hardware for implementation on devices such as FPGAs and ASICs.