A Hardware Accelerator for Tomographic Reconstruction and 2D-Filtering

摘要

In this paper we present the design of a hardware-software system for algorithms of commonly used tomo-graphic reconstruction methods, as well as 2D-filtering. The algorithms represent a group of computationally intensive image processing algorithms requiring high throughput and real-time processing. Processor arrays used as non-programmable hardware accelerators for computationally intensive algorithms are typically specific to one algorithm. In our approach, we designed a processor array which can calculate different equations with low architectural overhead. In particular, we propose one common parallel processor array for three different image processing algorithms. Furthermore, the basic functions of the array cells are typical operations of multimedia algorithms, too, such that more algorithms can be implemented on the processor array. The reconstruction system consists of the processor array, a software system to control data processing, and an interface to external hosts for remote observation and control. As a first prototype, we constructed a VLSI chip bearing a 32 x 2 array of general processor elements, and a board for connection to a PCI system.