An Embedded DRAM Macro Architecture for System-on-Chip

摘要

A new DRAM architecture for embedded applications is proposed to achieve high data rates at random row address accesses. Without page-like access mode, it activates a small block of memory arrays. Automatic precharge, which is done after prefetching read data or writing all data to cells at a time, and the small array activation shorten cycle time to enhance random row address access performance. A self-timed control circuit in the small array block makes each block to operate independently. In a 16-Mb DRAM macro, circuit simulation based on a 0.18-um DRAM process technology shows that the cycle time of the small cell array block can be shortened to 16-ns. It can accept row address access commands at every 4-ns interval using the small cell array blocks as independently accessible units. At a 250MHz clock, the macro with a 128-bit read bus and a 128-bit write bus provides a data rate of 8GB/s in consecutive simultaneous read and write operations in random row address accesses.