High Performance 20-T based Hybrid Full Adder using 90nm CMOS Technology

著录项

• 来源
  《Women Institute of Technology Conference on Electrical and Computer Engineering 》|2019年|192-195|共4页
• 会议地点 Dehradun Uttarakhand(IN)
• 作者

  Jyoti Kandpal; Abhishek Tomar; Kailash Pandey; Mayur Agarwal;

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• 作者单位

  G. B. P. U. A. T. Pantnagar Dept. of Electronics and Communication Engineering Pantnagar India;

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• 会议组织
• 原文格式 PDF
• 正文语种
• 中图分类
• 关键词

  Adders; Transistors; Delays; Logic gates; MOS devices; Simulation; CMOS technology;

  机译：加法器;晶体管;延误;逻辑门MOS器件;模拟; CMOS技术;