Architectural tradeoffs in synthesis of pipelined controls

摘要

Current synthesis approaches do not take into account the impactnof the underlying architecture during operations like scheduling andnbinding. This results in synthesis algorithms that can produce designsnonly for a single architecture. The design space that can be explored bynsuch a synthesis tool is limited. The authors examine threenarchitectures that have different control pipelining strategies. Theynderive the important constraints that these architectures impose on thenscheduling algorithm and propose an algorithm that incorporates thesenconstraints when producing a schedule. They also demonstrate throughnseveral experiments that by being able to synthesize for a given controlnpipeline architecture, they can provide designers with a wide range ofnarea-delay tradeoffs