On the implementation of an efficient performance driven generatorfor conditional-sum-adders

摘要

The authors present data structures and an efficient algorithmnrealizing efficient performance driven generation of integer adders. Thengenerator is parameterized in n, the operands' bitlength, and t_nn, the delay of the addition. It outputs an area minimal n-bitnadder of the conditional-sum type with delay ⩽t_n, if suchna circuit exists