The authors describe a procedure and a tool for ASIC synthesisnwith VHDL. They show that the functional level which they define and usenas the design input provides a synthesis level located between thensystem-level synthesis and the RT-level synthesis. The described designnand synthesis process is based on a complete methodology and the use ofnits functional model allows designers to describe their solutionsnaccording to two views: an organizational view which defines theninternal structure, and a behavioral view which describes the activitynof each function. Tools, mainly graphical, have been developed as an aidnto capture the design description. After that, a generator is used tonobtain the complete VHDL model at a RT-level model which is simulatablenand synthesizable. Such a tool leads to obtaining of ASIC prototypesnefficiently and in an incremental manner. Results for some ASICsndesigned by the authors are given to illustrate the benefit of thenproposed method and the significance of the functional level
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