On self-checking design of CMOS circuits

摘要

A technique that enables the design of total self checking (TSC)nFCMOS circuits for all realistic defects that may occur in VLSI circuitsnis discussed. The resulting area overhead is very low. The technique isnunable to detect multiple defects which include the weak transistors.nThis condition can be alleviated by adding more weak transistors innparallel to the existing ones. This redundancy does increase thenoverhead, but may be justifiable in certain cases. Simulation resultsnshow the introduction of a small delay in the circuit due to the twonweak transistors. This delay can be further minimized by proper choicenof the transistor sizes. The defects covered by this technique and thenlow overhead makes it practical for self checking VLSI circuit design