DLS: A scheduling algorithm for high-level synthesis in VHDL

摘要

Dynamic loop scheduling, an algorithm that can efficientlynschedule large, control-flow dominated designs, written in VHDL isnpresented. It compares favorably with results produced by otherncontrol-flow oriented approaches such as path-based scheduling, butnavoids the path explosion problem. In addition, the VHDL accepted by thenscheduler is quite comprehensive, including nested branches, loopsn(whose conditions can be compounded), loop exit statements and procedurencalls. The algorithm forms an integral part of the AMICAL data-pathncompiler