首页> 外文会议> >DLS: A scheduling algorithm for high-level synthesis in VHDL
【24h】

DLS: A scheduling algorithm for high-level synthesis in VHDL

机译:DLS:VHDL中高级综合的调度算法

获取原文

摘要

Dynamic loop scheduling, an algorithm that can efficiently schedule large, control-flow dominated designs, written in VHDL is presented. It compares favorably with results produced by other control-flow oriented approaches such as path-based scheduling, but avoids the path explosion problem. In addition, the VHDL accepted by the scheduler is quite comprehensive, including nested branches, loops (whose conditions can be compounded), loop exit statements and procedure calls. The algorithm forms an integral part of the AMICAL data-path compiler.
机译:提出了动态循环调度,该算法可以有效地调度以VHDL编写的大型控制流主导设计。与其他面向控制流的方法(例如基于路径的调度)产生的结果相比,它具有优势,但避免了路径爆炸问题。此外,调度程序接受的VHDL非常全面,包括嵌套分支,循环(可混合其条件),循环退出语句和过程调用。该算法构成AMICAL数据路径编译器的组成部分。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号