Circuit activity driven multilevel logic optimization for low powerreliable operation

摘要

The problem of optimization of multilevel combinational logic tonachieve low power dissipation as well as low area is considered whereinnit is assumed that static CMOS gates are used. Given a multilevelnBoolean network as a collection of functions, the system determines annew function at a time, adds it to the collection and expresses thenexisting functions in terms of it. In selecting the new function theneffect on power dissipation as well as area are considered. The authorsndescribe an efficient implementation of a general algorithm to computenexpected number of transitions per unit time at circuit nodes. Thesennumbers are in turn used to compute power dissipation. A prototypenmultilevel logic optimization system has been implemented. Results arengiven for a selection of benchmark examples