Power estimation for high level synthesis

摘要

Techniques for rapidly and accurately estimating power consumptionnbased on high level descriptions of system architectures are described.nThis approach, based on stochastic modeling of bus statistics, achievesnthe accuracy traditionally associated with gate and circuit levelnestimation tools while exploiting the reduced computational complexitynoffered by the architectural level of abstraction. The results presentednindicate an estimation accuracy within 9.4% of gate level simulations,nwhile existing high level techniques can be off 80% or more