首页> 外文会议>Symposium on Ultrathin SiO_2 and High-K Materials for ULSI Gate Dielectrics held April 5-8, 1999, San Francisco, California, U.S.A. >Comparison of valence-band tunneling in pure SiO_2, composite SiO_2/Ta_2O_5, and pure Ta_2O_5, in mosfets with 1.0 nm-thick SiO_2-equivalent gate dielectrics
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Comparison of valence-band tunneling in pure SiO_2, composite SiO_2/Ta_2O_5, and pure Ta_2O_5, in mosfets with 1.0 nm-thick SiO_2-equivalent gate dielectrics

机译:SiO_2等效栅电介质厚度为1.0 nm的MOSFET中纯SiO_2,复合SiO_2 / Ta_2O_5和纯Ta_2O_5的价带隧穿的比较

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摘要

The gate tunneling current in cultrathin gate dielectric NMOSFETs with positive gate bias is due to the tunneling of electrons from the conduction and valence bands of the substrate. Valence-band electrons tunnel from the substrate of NMOS devices when the valence-band edge in the substrate rises above the conduction-band edge in the substrate. This paper reports experimental trends in the contribution of valence-band electrons tunneling to the gate current of NMOSFETs with gate oxides composed of pure SiO_2. The large gate tunneling current can be reduced by replacing the conventional SiO_2 gate dielectric with alternative dielectrics with larger dielectric constants. This paper reports the effect of replacing SiO_2 with alternative dielectrics on the contribution of valence-band electron tunneling to the gate current. Simulations are carried out for composite SiO_2/Ta_2O_5 gate dielectric structures.
机译:具有正栅极偏置的晶闸管栅极电介质NMOSFET中的栅极隧穿电流归因于电子从衬底的导带和价带中隧穿。当衬底中的价带边缘上升到衬底中的导带边缘之上时,价带电子从NMOS器件的衬底隧穿。本文报道了价带电子隧穿对具有纯SiO_2组成的栅极氧化物的NMOSFET栅极电流的贡献的实验趋势。通过用具有较大介电常数的替代电介质代替传统的SiO_2栅极电介质,可以减小大的栅极隧穿电流。本文报道了用替代电介质代替SiO_2对价带电子隧穿对栅极电流的影响。对复合SiO_2 / Ta_2O_5栅介电结构进行了仿真。

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