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Electrical breakdown in a two-layer dielectric in the MOS structure

机译:MOS结构中两层电介质中的电击穿

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摘要

The formation of interfacial oxide between high-k and Si creates a two-layer dielectric in the MOS structure. In this paper, we present a model to describe electrical breakdown in the two-layer dielectric. Depending on the thickness ratio of the two dielectric layers, electrical breakdown can occur either in one dielectric after the other or simultaneously. In the case of one-by-one breakdown, the current through the two-layer dielectric shows three regimes with applied voltage: tunneling through two layers, tunneling through one layer, and breakdown for both layers. Our model has been compared with experimental data obtained from the HfO_x/SiO_2 MOS structure, and a good agreement is achieved. This model can be used to estimate either the thickness, breakdown field, or dielectric constant of each of the two dielectric layers. It can also predict the overall breakdown voltage for different combinations of dielectric layers. When combined with C-V measurements, more information about the two-layer dielectric is obtained.
机译:在高k和Si之间形成界面氧化物会在MOS结构中形成两层电介质。在本文中,我们提出了一个模型来描述两层电介质中的电击穿。取决于两个介电层的厚度比,电击穿可以在一个介电层之后在另一个介电层中发生,或者同时发生。在一对一击穿的情况下,流经两层电介质的电流在施加电压的情况下显示出三种状态:隧穿两层,隧穿一层以及两层击穿。我们的模型已与从HfO_x / SiO_2 MOS结构获得的实验数据进行了比较,并取得了良好的一致性。该模型可用于估计两个介电层中每个介电层的厚度,击穿场或介电常数。它还可以预测介电层不同组合的总击穿电压。与C-V测量结合使用时,可以获得有关两层电介质的更多信息。

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