EFFICIENT IMPLEMENTATION OF RECENT STREAM CIPHERS ON RECONFIGURABLE HARDWARE DEVICES

摘要

Stream ciphers have the reputation to be very efficient when implemented in hardware, much more efficient than any block cipher. However, although plenty of papers and books claim it, few results of hardware implementations of stream ciphers are available. In this paper, we provide FPGA implementation results of recent stream ciphers in order to evaluate their actual hardware efficiency. In addition, we compare these results with those of standard block ciphers (AES, 3DES, Rijndael, Misty 1, ...). The selected stream, ciphers are LILI-II, Helix and SNOW 2.0 and the implementation platform is a Virtex-II FPGA from Xilinx. On the basis of these results, it may be argued that while present stream ciphers allow us to obtain efficient implementations, they are not overwhelm,-ingly more efficient, than block ciphers. In general, their efficiency is comparable. However, stream ciphers are made of arguably low cost primitives which could provide really compact designs if correctly combined together.