Vienna Univ. of Technol., Vienna;
CMOS integrated circuits; MMIC amplifiers; SRAM chips; comparators (circuits); delays; error statistics; CMOS comparator; SRAM; bit rate 40 Gbit/s; clocked regenerative comparators; cross-coupled CMOS inverter; delay time; frequency 1.4 GHz; frequency 4 GHz; frequency 500 MHz; frequency 6 GHz; frequency 7 GHz; frequency 700 MHz; latch-type sense amplifier; low-voltage swing; power 1.3 mW; power 2.65 mW; power 350 muW; power 47 muW; size 0.11 mum; size 0.18 mum; size 65 nm; time 119 ps; transistor; voltage 0.5 V; voltage 0.6;
机译:电荷控制延迟元件可在1.2V,65nm CMOS中实现广泛的线性功率高效MPCG-MDLL
机译:具有65nm CMOS复用gm级的1.2V高转换增益混频器
机译:13.5-GB / S 5-MV灵敏度26.8-PS-CLK-OUT延迟三锁式前闩型动态比较器,28-NM CMOS
机译:具有改进闩锁的65nm CMOS比较器,实现0.6V的1.2V和700MHz /47μW的7GHz / 1.3mW
机译:低功耗高速低偏移完全动态CMOS锁存器
机译:0.18 µm CMOS工艺中的高速,低偏移动态锁存比较器的设计
机译:0.6V倍压器和时钟比较器,用于65nm CmOs中基于相关的脉冲无线电UWB接收器