Optimization and Implement Technique for Test Generation in the Design of BIST Architecture

摘要

This paper presents how to optimize test patterns according to the VHDL file of a PCB or a chip in the design of Built-in Self Test(BIST),so that the test-application time can be reduced to make BIST more practical while the needed fault coverage satisfied. Three optimizing manners have been discussed. They are man-made optimum method, least probability method and automatic generation method by EDIF file, and the last method has been specifically researched. On the basis of such researches some architectures of test pattern generator for BIST are designed and verified by simulation and implement in FPGA. The results indicate that the optimization of test patterns is related to both the methods and the architectures of the test pattern generator.